`timescale 1ns/1ps

module tb_flow_led();

reg sys_clk;
reg sys_rst_n;
wire [3:0] led;

flow_led u_flow_led(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    .led(led)
);

always #10 sys_clk = ~sys_clk;

initial begin
    sys_clk <= 1'b0;
    sys_rst_n <= 1'b0;

    #500

    sys_rst_n <= 1'b1; 
end

endmodule